1. Field of the Invention
The invention relates to simulation of charged device model (“CDM”) electrostatic discharge (“ESD”) events for a circuit and designing remedies therefore. More specifically, the improved simulation helps identify CDM ESD events that may damage core circuits of a circuit under test. Automated design tools may remedy the cause of the simulated circuit damage.
2. Discussion of Related Art
A frequent cause of failure in electronic circuit designs stems from ESD events. ESD events can generate substantial current flows and corresponding voltages within and application circuit that may easily damage a circuit design if left devoid of any protective measures. Thus, it is common for circuit designers to include ESD protection components for some circuitry in an application circuit design. Typically, such remedial components are added to circuits of the application design that are exposed to the external environment of the application circuit design. Such externally exposed circuits are susceptible to damage from ESD events. Thus, ESD clamp circuits and other familiar electronic designs are common for a circuit design engineer to utilize for all externally exposed circuit components of an application circuit design. Examples of externally exposed circuits are I/O circuits in which signals are exchanged between the application circuit and neighboring devices. As used herein, “core circuits” or “core components” refer to components of an application circuit design that are not I/O circuits.
The presumption of designers has generally been that if the externally exposed circuits of the application design are protected from damage by ESD events, then the other components of the application design (e.g., core components not generally externally exposed) will also be protected. The presumption assumes that since the damaging ESD current and voltage will be shunted away at the externally exposed circuits, then the core components will be safeguarded.
One particular type of ESD event has been widely recognized as a common type of event—typical of real world ESD events that frequently damage application circuits. The charged device model (“CDM”) is now widely accepted as an accurate model of real world ESD events that frequently damage application circuits. A wide variety of testing systems and tools have been developed to aid application circuit designers and fabricators in generating such CDM ESD events for controlled, repeatable, robust testing of an application circuit's immunity to such events. Such test systems actually generate CDM ESD events in a controlled, repeatable manner so that actual application circuits may be tested in accordance with standardized CDM ESD conditions. A JEDEC specification for such CDM ESD testing is well known to those of ordinary skill in the art in readily available at www.jedec.org.
A problem has been noted during CDM ESD testing wherein core circuits of an application circuit design are inexplicably damaged despite adherence to design principles that provide ESD protection for externally exposed circuits (e.g., non-core circuits) in the application circuit design. For example, where voltage and current from an ESD event are properly blocked or shunted by ESD clamps or other ESD protection circuits applied to externally exposed circuitry, core circuits internal to the application circuit design may none the less be inexplicably damaged. Current design tools and simulation techniques have been incapable of addressing this collateral damage to core circuits caused by real ESD events and/or caused by ESD testing systems.
It is evident from the above discussion that a need exists for improved design tools and simulation tools to remediate an application circuit design to avoid such damage and to predict design flaws that may cause such damage in an application circuit design.